Integrated circuits typically include circuit blocks that are used to implement a variety of functions. When signals need to be transmitted to different circuit blocks within an integrated circuit, the integrated circuit typically includes a clock network to ensure proper synchronization between the different circuit blocks. As data signals are transmitted to different parts of the integrated circuit (IC), clock signals may also be transmitted through a clock network within the integrated circuit to the different circuit blocks. In a synchronous design, clock signal distribution through a balanced clock network ensures that valid data signals are captured at every circuit block (e.g., flip-flops, latches, etc.) that forms part of the IC design.
However, if different clock networks in an IC have different signal propagation characteristics, the clock signals may not arrive at all of the circuit blocks at the same time. For example, a clock signal may be routed through a path with higher or lower resistance, capacitance, or driver strength caused by manufacturing variations that differ from chip-to-chip resulting in clock skew or misalignment.